Semiconductor / High Tech
SEMICONDUCTOR SCHEDULING OVERVIEW
As the use of electronics pervades more into everyday life in the form of computers, mobile phones, tablets etc., there is immense pressure on the semiconductor manufacturers to increase product variety, reduce delivery times and maintain high throughput. Due to rapid development, the industry is moving towards fully automated manufacturing systems. High volumes and increasing product variety make building to demand a complex proposition. The manufacturing plant must be flexible. Equally important is an effective planning and scheduling system to manage the complexity.
Key challenges facing semiconductor fabs are technological advancement, shorter product life cycles, meeting delivery commitments, being cost competitive and maintaining high throughput. From 300 mm (12 in) the industry is aiming to move to the 450 mm wafer size. At the same time line widths have been reduced from 65 nm to 22 nm, with 14 nm scale devices shipped in 2014 and objectives of further reduction. Large capital investments are necessary to automate the production of semiconductor chips from beginning to end.
These technological advances are associated with higher capital investments. However, from a business perspective semiconductor fabs are required to produce smaller lots of chips, in response to shorter lifecycles seen in consumer electronics. The logic is that a fab that can produce smaller lots more easily can efficiently switch its production to supply chips for a variety of electronic devices. Another important goal is to reduce fabrication time by reducing the waiting time between processing steps thus improving throughput and OEE (Overall Equipment Effectiveness) and reducing cost per lot. Synchronization of scheduling within and across the different areas of a fab and changeover/setup time optimization is key to reducing waiting times and improving throughput.
Optessa products can support semiconductor planning and scheduling requirements, from the level of a fab to a specific Frontend area, such as Photolithography and Diffusion or Backend area such as Test and Assembly. For more information please take a look at the semiconductor brochure available on the DOWNLOADS PAGE.
Semiconductor scheduling has a unique combination of requirements, including:
- Large number of process flows with complex routing
- Highly variable process times
- Re-entrant flows
- Batch operation
- Changeovers / set-up times
- Machine failures / downtimes
- Defective lots / reclassification
- Tool dependencies
- Resources like reticles
- Support of real-time rescheduling
- Performance evaluation & simulation
Optessa features to address the above requirements:
- Out of the box functionality to model the requirements
- Near optimal solutions generated by powerful proprietary algorithms
- Fast execution to support rapid scheduling and rescheduling
- Evenly favorable solution across entire schedule
- Powerful representation model for all types of area & tool configurations
- Comprehensive set of rules and constraints handled
- Native rescheduling capabilities
- Configurable system: data dictionary, parameter tables
- Scripting for further process customization
- “Light touch”: can be integrated & embedded with existing MES / Controller / Dispatch systems
- Enhance “What Next” and “Where Next” functionalities with true real-time optimization